1. Field
The present disclosure relates generally to an interface between a host processor and a peripheral device such as a camera and, more particularly, to improving clock generation for double data rate data transfer on an N-wire communication interface.
2. Background
Manufacturers of mobile devices, such as cellular phones, may obtain components of the mobile devices from various sources, including different manufacturers. For example, an application processor in a cellular phone may be obtained from a first manufacturer, while the display for the cellular phone may be obtained from a second manufacturer. The application processor and a display or other device may be interconnected using a standards-based or proprietary physical interface. For example, a display may provide an interface that conforms to the Display System Interface (DSI) standard specified by the Mobile Industry Processor Interface Alliance (MIPI).
In one example, a multi-signal data transfer system may employ multi-wire differential signaling such as 3-phase or N-factorial (N!) low-voltage differential signaling (LVDS), transcoding (e.g., the digital-to-digital data conversion of one encoding type to another) may be performed to embed symbol clock information by causing a symbol transition at every symbol cycle, instead of sending clock information in separate data lanes (differential transmission paths). Embedding clock information by transcoding is an effective way to minimize skew between clock and data signals, as well as to eliminate the necessity of a phase-locked loop (PLL) to recover the clock information from the data signals.
The capabilities and functionality of mobile devices continues to grow and there is a resultant demand for ever-increasing bandwidth between components within mobile devices and the like. Accordingly, there exists an ongoing need for optimized communications in general and improved reliability of data transfer on multi-signal wire communication links.